1. Field of the Invention
The present invention relates to a High Voltage Stress (“HVS”) test circuit for semiconductor devices and, more particularly, to an HVS test circuit for decoders, the HVS test circuit having a substantially reduced number of high supply voltage transistors.
2. Description of the Related Art
Typically, a test is performed during manufacture of a semiconductor device. Specifically, the test operates a semiconductor element of a manufactured semiconductor device to quickly test electrical characteristics and functional characteristics thereof, as well as to distinguish acceptable products from unacceptable products. Furthermore, the electrical and/or functional characteristics and yield of products, such as the semiconductor device, can be substantially improved by collecting and analyzing test data from the test and applying the test data to modify a manufacturing process of the products.
For example, in an HVS test, for example, one or more defects (or potential defects) can be discovered by applying stress to two ends of an insulating film of an MOS transistor of the semiconductor device. Specifically, in the HVS test, a high voltage is forcibly applied to the two ends of the insulating film. As a result, defects are discovered and a reliability of products is substantially improved by preemptively eliminating potential defects, for example.
FIG. 1 is a schematic diagram of a 1-bit n-channel metal oxide semiconductor (“NMOS”) of the prior art. Semiconductor devices typically include various types of decoders, such as the 1-bit NMOS decoder shown in FIG. 1, for example. In operation in a normal mode, the 1-bit NMOS decoder shown in FIG. 1 generates one of two input voltage levels V11 and V12 as a voltage level of an output signal DOUT1, based on a logic state of digital data DH applied to the transistor 12. As shown in FIG. 1, an inverted digital signal DHB, which is an inverted digital data of the digital data DH, is applied to the transistor 11.
To conduct an HVS test of the transistors 11 and 12 of the decoder, within a short period of time, the digital data DH and the inverted digital data DHB must be applied at a high supply voltage HVDD when the two input voltage levels V11 and V12 are maintained at a ground voltage VSS.
In addition, to conduct the HVS test, an HVS test circuit is contained in a semiconductor device. Specifically, in normal mode, the digital data DH and the inverted digital data DHB are provided by the HVS test circuit to have opposite logic states (based on a logic state of input data), while the digital data DH and the inverted digital data DHB are supplied at a high supply voltage HVDD (regardless of a logic state of the input data) in an HVS test mode.
FIG. 2 is a schematic diagram of an HVS test circuit according to the prior art. As shown in FIG. 2, the HVS test circuit of the prior art includes an internal data generation unit 110 for generating both internal data IDI and inverted internal data IDIB based on input data DI, and a level shifter 130 for generating both output data ODI and inverted output data ODIB by level-shifting the internal data IDI and the inverted internal data IDIB to the high supply voltage HVDD. Thus, the low supply voltage LVDD is used in the internal data generation unit 110, while the high supply voltage HVDD is used in the level shifter 130.
Meanwhile, the level shifter 130 is typically implemented using six transistors 131-136 using the high supply voltage HVDD, as shown in FIG. 3, which is a schematic diagram of a level shifter according to the prior art. Specifically, a p-channel metal oxide semiconductor (“PMOS”) transistor 131 and a PMOS transistor 132 pull up the output data ODI and the inverted output data ODIB to the high supply voltage HVDD in response to a pulling down of the inverted output data ODIB and the output data ODI. In addition PMOS transistors 133 and 134 function as resistances to reduce a short-circuit current which may be generated during switching of the output data ODI and the inverted output data ODIB. Additionally, an NMOS transistor 135 and an NMOS transistor 136 pull down the output data ODI and the inverted output data ODIB to a ground voltage VSS in response to the pulling up of the inverted output data ODIB and the output data ODI.
Referring again to FIG. 2, the HVS test circuit further includes a test response unit 150 for generating digital data DH and inverted digital data DHB based on the output data ODI and the inverted output data ODIB. The test response unit 150 typically includes two logical sum gates 151 and 152. In HVS test mode, in which a test mode signal VTEST is activated to a high logic state, the two logical sum gates 151 and 152 control the digital data DH and the inverted digital data DHB so that they have the high logic state regardless of logic states of the output data ODI and the inverted output data ODIB. Further, each of the two logical sum gates 151 and 152 is generally implemented using six transistors 21-26, as shown in FIG. 4, which is a schematic diagram of a logical sum gate according to the prior art. The test response unit 150 uses the high supply voltage HVDD and receives first and second inputs IN1 and IN2, respectively, corresponding to the output data ODI and the inverted output data ODIB, respectively (FIG. 2), for example, and outputs an output signal OUT, corresponding to the digital data DH or the inverted digital data DHB (FIG. 2), for example, as shown in FIG. 4.
However, a MOS transistor using the high supply voltage HVDD requires a considerably large layout area, as compared to a MOS transistor using the low supply voltage LVDD, due to leakage current being equal to or less than a threshold voltage of the associated MOS transistor. As a result, a reduction of a number of MOS transistors which use the high supply voltage HVDD is required, to substantially reduce a layout area, e.g., a size, of a semiconductor device according to an exemplary embodiment of the present invention.